Oxide semiconductors, first commercialized as thin-film-transistor (TFT) backplanes for AMOLED and LCD displays, are now being reconsidered as channel materials for vertically integrated 3D memory. This transition is far from a simple change of substrate: three-dimensional topography, stringent variability control, interface-limited transport, and integration-driven reliability impose constraints that conventional physical-vapor deposition cannot satisfy. Atomic layer deposition (ALD), through its self-limiting surface chemistry, offers a distinct pathway to meet these constraints via conformal growth on high-aspect-ratio structures and atomic-level control of thickness, composition, and interfaces.

In this talk, I will revisit the atomic-scale design principles that have guided my group's ALD oxide-semiconductor research over the past two decades and extend them toward the next stage of display-to-semiconductor convergence. Three practical levers will be discussed: (1) composition and stacking-sequence control in multi-cation oxides such as In-Ga-Zn-O and In-Sn-Ga-O, using ALD super-cycles and atomically-ordered stacking to tune carrier transport, mobility, and process-window uniformity; (2) crystallinity and defect engineering, where the trade-off between mobility and bias/thermal stability is governed by phase evolution, hydrogen behavior, and oxygen-related defects at the nanometer scale; and (3) interface and integration engineering (dielectric/channel and contact interfaces, hydrogen diffusion barriers, and thermal-budget management) required for compatibility with high-temperature, highly-stacked memory architectures such as 3D V-NAND and DRAM.

Building on these levers, I will introduce recent efforts toward high-temperature-stable amorphous and poly-crystalline oxide channels, hybrid oxide/poly-Si channels for highly stacked NAND, p-type oxide channels for vertically-stacked complementary FETs, and atomic-layer etch-back processes for sub-5-nm channel scaling. I will close with a forward-looking view on how continued advances in ALD process chemistry, interface engineering, and atomic layer etching may open new possibilities for oxide-semiconductor channels in future 3D systems. As oxide semiconductors move from display backplanes to the crossroads of display and semiconductor technology, LLM- and ML-assisted analysis of the growing literature may help clarify persistent mobility–stability trade-offs and point toward promising material and process directions (from precursor chemistry to thermally-robust p-type and amorphous/crystalline channels) charting a path toward scalable oxide-semiconductor channels for next-generation vertically-integrated electronics

Area-selective atomic layer deposition(AS-ALD) is a highly promising bottom-up nanomanufacturing strategy and is regarded as a key technology for next-generation semiconductor fabrication. However, achieving robust and long-lived selectivity remains a major challenge due to inhibitor degradation, precursor penetration, thermal desorption, and defect-induced nucleation. To unify the understanding of these selectivity evolution mechanisms, a four-dimensional physical framework integrating lateral, vertical, and temporal dimensions is established to describe inhibitor-coverage decay and selectivity evolution during deposition. Based on this framework, phenomena including precursor penetration within inhibitor layers, selective deposition of multicomponent oxides, selectivity degradation induced by inhibitors with different chain lengths, dynamic evolution of inhibitor coverage during thermal treatment and ALD cycling, and the high temperature stability of aromatic thiol inhibitors are systematically discussed. These studies reveal the intrinsic correlations among molecular structure, interfacial reactions, and selectivity failure. In addition, inhibitor-assisted AS-ALD on metal, oxide, nitride, and silicon substrates is comprehensively analyzed, and a taxonomy of selectivity failure modes is established to correlate molecular scale degradation pathways with experimentally observable selectivity losses. Furthermore, key challenges for practical device integration, including complex topography, lateral overgrowth, high-temperature processing, and deep-hole structures are analyzed, and practical design principles for long-lifetime inhibitors and scalable ASD process optimization are summarized. Future directions include the development of multicomponent inhibitor libraries, process-material co-design strategies, and closed-loop in situ characterization platforms for dynamic monitoring and predictive control of selectivity evolution. Overall, this work provides systematic mechanistic understanding and practical design guidelines for predictive selectivity control and scalable atomic-precision manufacturing in next-generation integrated circuits.